This invention relates to a constant voltage circuit containing a MOS type integrated circuit and, more particularly, to an improvement to delete the change of an output voltage due to a channel length modulation effect of a MOS transistor.
An example of a conventional constant voltage circuit is shown in FIG. 1. This constant voltage circuit comprises three P-channel MOS transistors P1, P2, P3, two N-channel MOS transistors N1, N2 and two resistors R1, R2.
In the constant voltage circuit of an arrangement as shown in FIG. 1, a current flowing in series through the MOS transistor P1, the resistor R1 and the MOS transistor N1 is I1, a current flowing in series through the MOS transistors P2 and N2 is I2, and a current flowing in series through the MOS transistor P3 and the resistor R2 is I3.
The operation of the constant voltage circuit of FIG. 1 will be simply described. The channel widths of the MOS transistors P1, P2, P3, N1, N2 are respectively WP1, WP2, WP3, WN1, WN2, and the channel lengths of these MOS transistors P1, P2, P3, N1, N2 are respectively LP1, LP2, LP3, LN1, LN2. At this time, the relationship among the LP1, LP2, LP3, LN1, LN2 are set to LP1=LP2=LP3, and LN1=LN2.
The gates of the MOS transistors P1 and P2 are commonly connected, the gate of the MOS transistor P2 is connected to the drain of the same MOS transistor P2, and both the MOS transistors constitute a current mirror circuit. And, the following equation is satisfied in the relationship among the WP2, WP1, I2 and I1: EQU WP2/WP1=I2/I1 (1)
Further, the MOS transistors N1, N2 are together operated in a weak inversion region. The gradient of the drain current (logarithm) characteristics to the gate voltage in the weak inversion region is assumed as 1/K. The drain currents of the N-channel MOS transistors when the gate voltage of the N-channel MOS transistor are Vg1. Vg2 are respectively Id1, Id2, the following equation is obtained: EQU 1/K={1n(Id1)-1n(Id2)}/(Vg1-Vg2) (2)
Accordingly, the following equation is obtained: EQU Id1/Id2=exp{(Vg1-Vg2)/K} (3)
That is, when the gate voltages of the N-channel MOS transistors N1, N2 are V11, V12, the following equations are satisfied via I0/L set as a constant. EQU I1=(I0/L).multidot.WN1.multidot.exp{V11/K} EQU I2=(I0/L).multidot.WN2.multidot.exp{V12/K}
Accordingly, EQU I1/I2=(WN1/WN2).multidot.exp{(V11-V12)/K} (4)
Hence, the following equation is obtained: ##EQU1## Accordingly, from the equations (1) and (5), the following equation is induced. EQU I1.multidot.R1=K.multidot.1n{(WP1/WP2).multidot.(WN2/WN1)} (6)
In the equation (6), the K is determined according to the manufacturing process, and the I1 is set to a desired value by suitably determining the values of the WP1, WP2, WN1, WN2 and R1. At this time, since the equation (6) does not have a parameter depending upon a power source voltage, a constant-current operation is theoretically realized for the power source voltage. Further, since the MOS transistor P3 constitutes a current mirror circuit together with the MOS transistor P2, WP2/WP1=I2/I1, WP3/WP2=I3/I2 are satisfied, and the following equation is obtained: EQU WP3/WP1=I3/I1 (7)
Hence, the MOS transistor P3 is operated as a constant-current source for the power source voltage, and an output voltage Vout is given by the following equation: EQU Vout=I3.multidot.R2 (8)
More specifically, the output voltage Vout does not depend upon the power source voltage VDD but makes it possible to be a constant value.
In the conventional constant voltage circuit, it has been described that the output voltage Vout of the constant value can be always obtained without depending upon the power source voltage VDD. However, this is the case that the channel length modulation effect of the MOS transistor is not considered at all. The channel length modulation effect of the MOS transistor means, as shown in FIG. 2, the phenomenon that, as a voltage VDS between the drain and the source increases, a current IDS between the drain and the source increases. More specifically, in the saturated region of the MOS transistor (Vds.gtoreq.VGS-VTH) (where the VTH is a threshold voltage), the IDS has a gradient depending upon the VDS according to the channel length modulation effect (In FIG. 2, the VGS show the two characteristics of VGS1 and VGS2).
Accordingly, in the conventional circuit shown in FIG. 1, P-channel and N-channel MOS transistor threshold voltages are VTHP, VTHN. Since the V11, V12 become near the VTHN, the gate voltage V2 of the P-channel MOS transistor P3 becomes near VDD-.vertline.VTHP.vertline. and the Vout becomes a set predetermined voltage as the power source voltage VDD increases, the VDSs of the MOS transistors P1, P3, N2 increase as the VDD increases. Therefore, channel length modulation effect takes places, and hence the I1, I2, I3 to be originally determined according to the ratio of the WP1, WP2, WP3 cause an error to occur. When the I1 increases due to the channel length modulation effect, the voltages drop of I1.R1 is increased, the gate bias of the MOS transistor N2 is shifted to the GND side, and hence it acts so as to suppress the I2. However, since the increased current due to the channel length modulation effect of the currents I1, I3 predominantly acted, the output voltage Vout given by the previous equation (8) becomes as follows when the current increase of the I3 is .DELTA.I3, EQU Vout=(I3+.DELTA.I3).multidot.R2 (9)
the output voltage Vout depends upon the power source voltage in the operating region A of the constant voltage circuit as shown in FIG. 3, and exhibits the characteristics that it becomes larger than the theoretical value. Normally, in the case of the Vout in the order of several volts, when the power source voltage changes at 1V, the output voltage Vout varies about several mV to 100 mV. This decreases the accuracy of the constant voltage output with the result that the reliability of the LSI is impaired.
Heretofore, to eliminate the malfunction, the channel lengths of the respective MOS transistors has been elongated to suppress the changes to the minimum limit. However, this method has a limit, and in this case, the occupying area of the constant voltage circuit on a semiconductor chip is increased.
It is therefore an object of the present invention to provide an accurate constant voltage circuit by reducing the influence of the channel length modulation effect of a MOS transistor.